 
module top(
  input sys_clk,
//  input key1,
  input key2,
  output led,
  
  //uart接口
  input uart_rxd,
  output uart_txd,

  //32u4
  input debug_rst,
  input debug_mosi, 
  output debug_miso,
  input debug_sck,
  output debug_ack,

  //ch341
  output ch341a_ack,
  output ch341a_miso,
  input ch341a_mosi,
  input ch341a_sck,
  input ch341a_cs2,
  input ch341a_cs1,
  input ch341a_cs0,
  
  //input cy_SCL,
  output cy_rst_out,
  inout [7:0] cy_D,
  inout [7:0] cy_B,
  output cy_IFCLK_out                     ,
  input cy_to_fpga_CTL0_FLAGA        ,
  input cy_to_fpga_CTL2_FLAGC        ,
  input cy_to_fpga_CTL1_FLAGB        ,
  input cy_to_fpga_A7_FLAGD          ,
  output  cy_from_fpga_RDY1_SLWR       ,//output
  output  cy_from_fpga_RDY0_SLRD       ,//output
  input cy_A0_INT0                   ,
  output cy_A1_INT1                   ,
  output  cy_from_fpga_A2_SLOE         ,//output
  input cy_A3_WU2                    ,
  //output  cy_from_fpga_A4_FIFOADR0     ,//output
  output  cy_from_fpga_A5_FIFOADR1     ,//output
  //output  cy_from_fpga_A6_PKTEND       ,//output
 
  output [7:0] debug,
  
  output spirom_clk,
  output spirom_mosi,
  output spirom_ncs,
  input spirom_miso,
  output spirom_nwp_io2,
  output spirom_nhold_io3,

  output w25q64_ncs,
  output w25q64_clk,
  inout w25q64_di_io0,
  inout w25q64_do_io1,
  inout w25q64_nwp_io2,
  inout w25q64_nhold_io3,
  
  //SDRAM 芯片接口
  output        sdram_clk_out,                //SDRAM 芯片时钟
  output        sdram_cke,                //SDRAM 时钟有效
  output        sdram_cs0_n,               //SDRAM 片选
  output        sdram_cs1_n,               //SDRAM 片选
  output        sdram_ras_n,              //SDRAM 行有效
  output        sdram_cas_n,              //SDRAM 列有效
  output        sdram_we_n,               //SDRAM 写有效
  output [ 1:0] sdram_ba,                 //SDRAM Bank地址
  output [12:0] sdram_addr,               //SDRAM 行/列地址
  inout  [15:0] sdram_data,               //SDRAM 数据
  output [ 1:0] sdram_dqm,                //SDRAM 数据掩码
 
  input hid_dat_n,
  input hid_clk_n,
  input hid_str_n,

  output audio_pwm,

  inout [7:0] ch375_d,
  input ch375_int,
  output ch375_a0,
  output ch375_cs,
  output ch375_rd,
  output ch375_wr,

  input   spi_MISO,        //     spi.MISO
  output  spi_MOSI,        //        .MOSI
  output  spi_SCLK,        //        .SCLK
  output  spi_CS,         //        .SS_n
 
  input flash_data0,
  output flash_sdo,
  output flash_sce,
  output flash_dclk,

  output ds1302_clk,
  inout  ds1302_dat,
  output ds1302_rst,
  
  output led_data_read,
  output led_data_write,
  output led_ins_read,

  //VGA接口                          
  output          vga_hs,         //行同步信号
  output          vga_vs,         //场同步信号
  output  [15:0]  vga_rgb         //红绿蓝三原色输出 
  
);
wire sys_rst_n;
assign sys_rst_n = key2 && locked_vga && locked_sdram && locked_cpu;
assign spirom_nwp_io2 = 1'b1;
assign spirom_nhold_io3 = 1'b1;

assign led = 0;
//`include "config.v"

wire vga_clk_25M;
wire vga_clk_65M;
wire clk_100m;
wire clk_100m_shift;
wire clk_cpu;
wire locked_vga;
wire locked_sdram;
wire locked_cpu;
//例化PLL, 产生各模块所需要的时钟
pll_clk u_pll_sdram(
  .areset	(~key2),
  .inclk0             (sys_clk),
  .c0                 (clk_100m),
  .c1                 (clk_100m_shift),
	.locked             (locked_sdram)
);
 
//例化PLL, 产生各模块所需要的时钟
pll_vga u_pll_vga(
  .inclk0             (sys_clk),
  .c0                 (vga_clk_25M),
  .c1                 (vga_clk_65M),
	.locked             (locked_vga)
);

wire clk_cpu1;
wire clk_cpu2;
//例化PLL, 产生各模块所需要的时钟
pll_cpu u_pll_cpu(
  .areset	(~key2),
  .inclk0             (sys_clk),
  .c0                 (clk_cpu1),
  .c1                 (clk_cpu2),
	.locked             (locked_cpu)
);
wire cpu_clk_sel;
lpm_mux	LPM_MUX_component (
			.data ({clk_cpu2, clk_cpu1}),
			.sel (cpu_clk_sel),
			.result (clk_cpu)
			);
defparam
	LPM_MUX_component.lpm_size = 2,
	LPM_MUX_component.lpm_type = "LPM_MUX",
	LPM_MUX_component.lpm_width = 1,
	LPM_MUX_component.lpm_widths = 1;
//myaltclkctrl myaltclkctrl_ins (
//.clkselect(cpu_clk_sel),
//.inclk0x(clk_cpu1),
//.inclk1x(clk_cpu2),
//.outclk(clk_cpu)
//);

//25Mhz
assign cy_IFCLK_out = clk_cy;
wire   cy_IFCLK_in  = ~clk_cy;
 
reg clk_cy;
always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    clk_cy <= 0;
  end else begin
    clk_cy <= ~clk_cy;
  end
end

//wire segled_clk;
//wire segled_dat;
//wire segled_str;
//assign debug[2:0] = {segled_clk,segled_dat,segled_str};
//wire [7:0] seg_data0;
//wire [7:0] seg_data1;
//wire [7:0] seg_data2;
//wire [7:0] seg_data3;
//seg_led_hex595 ins_seg_led_hex595(
//  .sys_clk(sys_clk), 
//  .sys_rst_n(sys_rst_n),
// 
//  .clk(segled_clk),
//  .dat(segled_dat),
//  .str(segled_str),
// 
//  .data0(debug32[7:0]),
//  .data1(debug32[15:8]),
//  .data2(debug32[23:16]),
//  .data3(debug32[31:24])
//);
 
wire [31:0] outpin32;

wire [7:0] debug8;
wire [31:0] debug32;

//assign debug = debug8;//{3'b0, debug_ack, debug_rst,   debug_mosi,    debug_miso,   debug_sck  };//debug8;//
//assign debug[0] = hid_dat;
//assign debug[1] = hid_clk;
//assign debug[2] = hid_str;

wire hid_dat = ~hid_dat_n;
wire hid_clk = ~hid_clk_n;
wire hid_str = ~hid_str_n;

wire [3:0] debug4;
wire dummy;
system system_inst(
  .clk      (clk_cpu),        //     clk_cpu
	.clk_50M  (sys_clk),
  .clk_100m(clk_100m),
  .clk_100m_shift(clk_100m_shift),
	
  .reset_n  (sys_rst_n),  //   reset.reset_n

  //.mycpu_uart_rxd (uart_rxd), //        .uart_rxd
  //.mycpu_uart_txd (uart_txd), //   mycpu.uart_txd

  .debug8         (debug8),    //        .debug
  .debug32        (debug32),   //        .debug0

  .sdram_clk_out (sdram_clk_out ),   // sdram_0.addr
  .sdram_cke     (sdram_cke     ),   //        .ba
  .sdram_cs0_n   (sdram_cs0_n    ),   //        .cas_n
  .sdram_cs1_n   (sdram_cs1_n    ),   //        .cas_n
  .sdram_ras_n   (sdram_ras_n   ),   //        .cke
  .sdram_cas_n   (sdram_cas_n   ),   //        .cs_n
  .sdram_we_n    (sdram_we_n    ),   //        .dq
  .sdram_ba      (sdram_ba      ),   //        .dqm
  .sdram_addr    (sdram_addr    ),   //        .ras_n
  .sdram_data    (sdram_data    ),   //        .we_n
  .sdram_dqm     (sdram_dqm     ),

  .myuart_rxd     (uart_rxd),     //  myuart.rxd
  .myuart_txd     (uart_txd),      //        .txd

  .hid_clk   (hid_clk ),
  .hid_dat   (hid_dat ),
  .hid_str   (hid_str ),

  .softspi_MISO        (spi_MISO),        //     spi.MISO
  .softspi_MOSI        (spi_MOSI),        //        .MOSI
  .softspi_SCLK        (spi_SCLK),        //        .SCLK
  .softspi_CS          (spi_CS),         //        .SS_n    
  
  .spirom_clk          (spirom_clk),
  .spirom_mosi         (spirom_mosi),
  .spirom_ncs          (spirom_ncs),
  .spirom_miso         (spirom_miso),

  .flash_data0(flash_data0),
  .flash_sdo  (flash_sdo  ),
  .flash_sce  (flash_sce  ),
  .flash_dclk (flash_dclk ),

  .debug_rst          (debug_rst ),
  .debug_mosi         (debug_mosi), 
  .debug_miso         (debug_miso),
  .debug_sck          (debug_sck ),
  .debug_ack          (debug_ack ),
  
  .ch341a_ack         (ch341a_ack ),
  .ch341a_miso        (ch341a_miso),
  .ch341a_mosi        (ch341a_mosi),
  .ch341a_sck         (ch341a_sck ),
  .ch341a_cs2         (ch341a_cs2 ),
  .ch341a_cs1         (ch341a_cs1 ),
  .ch341a_cs0         (ch341a_cs0 ),
  
  .cy_D(cy_D),
  .cy_B(cy_B),
  .cy_rst_out(cy_rst_out),
  //.cy_SDA(cy_SDA)       ,
  .cy_IFCLK(cy_IFCLK_in),
  .cy_to_fpga_CTL0_FLAGA(cy_to_fpga_CTL0_FLAGA),
  .cy_to_fpga_CTL2_FLAGC(cy_to_fpga_CTL2_FLAGC),
  .cy_to_fpga_CTL1_FLAGB(cy_to_fpga_CTL1_FLAGB),
  .cy_to_fpga_A7_FLAGD(cy_to_fpga_A7_FLAGD),
  .cy_from_fpga_RDY1_SLWR(cy_from_fpga_RDY1_SLWR)       ,//output
  .cy_from_fpga_RDY0_SLRD(cy_from_fpga_RDY0_SLRD)       ,//output
  .cy_from_fpga_A2_SLOE(cy_from_fpga_A2_SLOE)         ,//output
  .cy_A0_INT0(cy_A0_INT0)                   ,
  .cy_A1_INT1(cy_A1_INT1)                   ,
  .cy_A3_WU2(cy_A3_WU2)                    ,
  //.cy_from_fpga_A4_FIFOADR0(cy_from_fpga_A4_FIFOADR0)     ,//output
  .cy_from_fpga_A5_FIFOADR1(cy_from_fpga_A5_FIFOADR1)     ,//output
  //.cy_from_fpga_A6_PKTEND(cy_from_fpga_A6_PKTEND)       ,//output

  .audio_pwm (audio_pwm),
  
  .ch375_d      (ch375_d  ),
  .ch375_int    (ch375_int),
  .ch375_a0     (ch375_a0 ),
  .ch375_cs_out (ch375_cs ),
  .ch375_rd     (ch375_rd ),
  .ch375_wr     (ch375_wr ),


  .w25q64_ncs       (w25q64_ncs      ),
  .w25q64_do_io1    (w25q64_do_io1   ),
  .w25q64_nwp_io2   (w25q64_nwp_io2  ),
  .w25q64_nhold_io3 (w25q64_nhold_io3),
  .w25q64_clk       (w25q64_clk      ),
  .w25q64_di_io0    (w25q64_di_io0   ),
  
  .ds1302_clk       (ds1302_clk),
  .ds1302_dat       (ds1302_dat),
  .ds1302_rst       (ds1302_rst),
  
  .led_data_read         (led_data_read),
  .led_data_write        (led_data_write),
  .led_ins_read          (led_ins_read),

  
    .blockvga(blockvga),
    .vga_mode(vga_mode),
    .read_line_base_addr (read_line_base_addr ),
    
    .read_line_req       (read_line_req       ),
    .read_line_ack       (read_line_ack       ),
	 .read_line_part      (read_line_part      ),
    .read_line_A_B       (read_line_A_B       ),
    .read_line_addr      (read_line_addr      ),
    
    .read_pixelA_data    (read_pixelA_data    ),
    .read_pixelB_data    (read_pixelB_data    ),
    .read_pixel_addr     (read_pixel_addr     ),
    .read_pixel_clk      (read_pixel_clk      ),
    
    
    .cursor_posX(cursor_posX),//0~1024
    .cursor_posY(cursor_posY),//0~1024
    .read_cursor_data(read_cursor_data),
    .read_cursor_addr(read_cursor_addr),//32 * 32
    .read_cursor_clk (read_cursor_clk ),
  
  .cpu_clk_sel (cpu_clk_sel),
  
  .dummy(dummy)
  
 );


  wire blockvga;
  wire vga_mode;
wire [15:0] read_line_base_addr;
    
 wire        read_line_req ;
 wire        read_line_ack ;
 wire        read_line_part; 
 wire        read_line_A_B ;
 wire [15:0] read_line_addr;
    
  wire [15:0] read_pixelA_data      ;//output [15:0] buff_readA_data,
  wire [15:0] read_pixelB_data      ;//output [15:0] buff_readB_data,
  wire  [9:0] read_pixel_addr       ;//input [9:0]   buff_readB_addr,
  wire        read_pixel_clk        ;//input         buff_readB_clk,


  wire  [9:0]  cursor_posX;//0~1023
  wire  [9:0]  cursor_posY;//0~1023
  wire [15:0] read_cursor_data;
  wire [9:0]  read_cursor_addr;//32 * 32
  wire        read_cursor_clk;
  

  vga_driver8m u_vga_driver8m(
    .sys_rst_n      (sys_rst_n),
    .vga_clk_25M(vga_clk_25M),
    .vga_clk_65M(vga_clk_65M),

    .blockvga(blockvga),
    .vga_mode(vga_mode),
    .read_line_base_addr (read_line_base_addr ),
    
    .read_line_req       (read_line_req       ),
    .read_line_ack       (read_line_ack       ),
	 .read_line_part      (read_line_part      ),
    .read_line_A_B       (read_line_A_B       ),
    .read_line_addr      (read_line_addr      ),
    
    .read_pixelA_data    (read_pixelA_data    ),
    .read_pixelB_data    (read_pixelB_data    ),
    .read_pixel_addr     (read_pixel_addr     ),
    .read_pixel_clk      (read_pixel_clk      ),
    
    
    .cursor_posX(cursor_posX),//0~1024
    .cursor_posY(cursor_posY),//0~1024
    .read_cursor_data(read_cursor_data),
    .read_cursor_addr(read_cursor_addr),//32 * 32
    .read_cursor_clk (read_cursor_clk ),

    .vga_hs         (vga_hs),
    .vga_vs         (vga_vs),
    .vga_rgb        (vga_rgb)
    
  );


endmodule
            

  